Optimization of Source Pocket Height on Source Pocket Half Hetero Dielectric Double Gate TFETs (SP-HHD-DG-TFET)
Abstract
Optimization of different electrical parameters are done by modifying the structure as well as using appropriate material in double gate tunnel FET (DG-TFET) for proper application of such devices. The simulation, using Silvaco TCAD on DG-TFET with source pocket (SP) of at the junction of source-channel within the n-channel along with the used of hetero-dielectric of and , high-k dielectrics at the gate near the source and in the remaining half part of the gate, near the drain i.e. half hetero dielectric (HHD) at the gate is done. The obtained electrical characteristics as well as calculate different physical parameters on the structure source pocket half DG-TFET (SP-HHD-DG-TFET) structure is studied using SILVACO ATLAS and explained with different phenomena of physics causing such behavior. The optimization of the height of the SP shows that the SP of height of shows ratio and sub-threshold swing (SS) to be and . Hence, the optimized length and the model is suggested be useful as a low-power and high speed devices.
References
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